The invention relates to decoding circuitry for addressing a memory circuit having a scan latch arrangement.
Computer and dedicated hardware circuits use RAM (Random Access Memory) to allow quick retrieval of stored data. This data may either be instructions forming part of a computer program or alternatively operand data to be manipulated. The data is stored in memory cells. For example, a typical SRAM memory consists of an array of memory cells having bit lines and word lines. A decoder circuit receives a binary address thereby selecting the relevant bit line and word line so that the appropriate memory cell can be read from or written to.
Many modern integrated circuits have scan latches connected to the inputs and outputs. The integrated circuit can be in a scan mode of operation whereby a known bit stream is loaded into each latch of a scan latch arrangement and then at a predetermined time, the latches may be clocked onto the inputs to the integrated circuit. In this manner, a technical person is able to efficiently perform certain tests on such a circuit.
Furthermore, in many decoder memory circuits there is an enable signal that is used to synchronise the non-inverting inputs with the inverting inputs, because an inverted signal passes through an inverting element and experiences a certain delay. The enable signal is used to only enable the decoder circuitry once both inputs have settled.
A requirement, for example on an SRAM circuit, is to disable the decoder circuitry during scan mode operation thus preventing multiple word lines from being activated, which corrupts memory cells. A known solution is to gate a scan mode signal with an enable signal so that the decoder is not enabled during scan mode and only enabled during the normal mode of operation when the enable signal is present. The problem is that the gate element introduces an additional unwanted delay period into the critical path of the decoding circuitry.
Therefore one of the aims of the preferred embodiments of the present invention is to prevent the decoder from activating word lines during scan-mode operation without introducing an unwanted delay into the critical path.
A distinction needs to be made between the delay purposefully introduced so as to synchronise the inverting and non-inverting inputs and the unwanted delay that occurs as a result of the gating arrangement inherent to the standard solution of disabling the decoder outputs during scan-mode operation.
According to one aspect of the invention there is provided a decoder for activating one of a plurality of output lines depending on a binary address received on a plurality of input lines each providing a respective inverted and non-inverted input which are synchronised by a decode signal, the decoder having a plurality of identical circuits each for driving one of said output lines, each circuit comprising: a plurality of serially connected switching elements between a first node and a second node, each switching element receiving an input from at least one of said respective inverted or non inverted input lines; pull-up means for pulling said first node to a high potential; an output driver connecting said first node to said output line; and a disable driver for driving said second node to a low or a high potential depending on the decoder""s mode of operation.
Preferably, each of the respective inverting inputs has an inverting element with a propagation delay and where a decode signal enables the decoder at intervals of said propagation delay thereby synchronising the received inverted and non-inverted inputs.
Preferably, wherein each input of the decoder circuit has a scan-latch and these are arranged in a chain to receive a known bit stream scanned through the latches during a scan mode of operation. Preferably, in the scan mode of operation the second node potential is driven high by the disable driver and when all the switching elements are switched on, said high potential is supplied to the first node where pull-up means prevent drops in potential across the switching elements from pulling the first node potential low. Preferably, wherein the output driver inverts the high potential on the first node thereby disabling the selected output line.
Preferably, wherein the pull-up means of the decoder circuit is used to connect the first node to a positive voltage supply. A first embodiment of the pull-up means comprises a full CMOS gate having a plurality of PMOS transistors, each transistor having the gate terminal connected to an input line. A second embodiment of the pull-up means comprises a PMOS transistor having its gate terminal connected to earth. A third embodiment of the pull-up means comprises a resistor.
According to another aspect of the present invention there is provided a method for operating a decoder for activating one of a plurality of output lines depending on a binary address received on a plurality of input lines each having an inverted and a non-inverted input which are synchronised by a decode signal, the decoder having a plurality of identical circuits each for driving one of said output lines, wherein the method for operating each circuit comprises: applying said respective inverted or non inverted inputs to a plurality of serially connected stacked switching elements between a first node and a second node; pulling said first node to a high potential using pull-up means; driving said output line with an output driver connected to said first node; and driving said second node to a high or low potential with a disable driver depending on the decoder""s mode of operation.